#include <arch/mmu.h>
#include <arch/cache.h>
#include <arch/cpu/soc/s3c2440.h>
#include <device.h>
#include <arch/machine.h>
#include <machine.h>
#include <uart.h>
#include <arch/io.h>
#include <config.h>
#include <errno.h>

static void qt2440_sdram_init(void)
{
	struct s3c2440_mem * __maybe_unused memctl = s3c2440_get_base_memctl();
	
#if ((CONFIG_FCLK_FREQ == 304000000) && (CONFIG_FCLK_HCLK_RATIO == 3))
	writel((2 << 24) | (0 << 26) | (0 << 27) ,&memctl->bwscon);	// BANK6: 32bit, not wait, not UB/LB
	writel((3 << 15) | (1 << 2) | (1 << 0), &memctl->bankcon[6]);	// BANK6: SDRAM, 9bit column address, TRCD=3 clocks
	writel((1 << 23) | (0 << 22) | (1 << 20) | (0 << 18) | (1257 << 0), &memctl->refresh);
	writel((1 << 7) | (0 << 5) | (1 << 4) | (1 << 0), &memctl->banksize);
	writel((0 << 9) | (0 << 7) | (3 << 4) | (0 << 3) | (0 << 0), &memctl->mrsrb6);
#endif
}

extern void s3c2440_clocks_init(void);

static void qt2440_machine_init(void)
{
	struct device *dev;
	struct uart_device *uart_dev;

	dcache_disable();
	mmu_disable();
	icache_invalidate_all();
	icache_enable();

	s3c2440_clocks_init();
	qt2440_sdram_init();
	
	dev = device_lookup_by_id(DEVICE_UART, -1);
	if (IS_ERR(dev)) {
		while (1);
	}
	uart_dev = dev->priv;
	uart_dev->init(dev);
}

static struct machine_arm_desc qt2440_desc = {
	.cpu_val	= 0x41009200,
	.cpu_mask	= 0xff00fff0,
};

MACHINE_START(QT2440)
	.init_machine	= qt2440_machine_init,
	.priv			= &qt2440_desc,
MACHINE_END

